1. Field of the Invention
The present invention relates generally to power-on circuits which provide a reset signal to a logic circuit in response to the application of power to the circuit. More specifically, the present invention relates to a power-on circuit adapted for use in CMOS integrated circuits.
2. Description of the Prior Art
Power-on reset circuits provide a reset signal to initialize flip-flops and other logic circuits in response to the application of power to the circuit. Conventional CMOS power-on circuits are designed to insure that a supply voltage sufficient to operate all of the devices in the circuit has been attained before a reset signal is provided. However, these power-on circuits are characterized by two undesirable characteristics. First, the supply voltage which must be attained before a reset signal is provided, i.e., the trip point, of these power-on circuits is typically much higher than the voltage needed for operation of the circuit. For instance, the Motorola MC14541 Programmable Timer specifies that a supply voltage of 8.5 volts is required to reset the circuit. However, threshold voltages for N and P-channel devices are approximately 1-2 volts, thus a supply voltage only slightly greater than 2 volts would be sufficient for proper operation of the circuit. Second, the power required by the conventional power-on circuits is greater than desired. For instance, the Motorola circuit appears to apply a steady state input to the output inverter which has a voltage equal to the supply voltage less a diode drop and a P-channel threshold. This voltage drop is sufficient to turn on both of the devices in the output inverter, which causes the inverter to draw an undesirable steady state DC current.